Reading circuit for a non-volatile memory
US6400607B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit having an array branch connected to a multi-level array memory cell; a reference branch connected to a reference memory cell; a current/voltage converter stage formed of a current mirror having a variable mirror ratio, connected to the array and reference branches, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated respectively to the currents flowing in the array branch and in the reference branch; and a comparator stage having a first and a second input connected to the array and reference nodes for comparing with one another the array and reference potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.