Memory device including isolated storage elements that utilize hole conduction and method therefor
US6400610B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 5, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jul 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is presented that utilizes isolated storage elements (200) in a floating gate structure, where tunneling holes (404) are used to program the device and tunneling electrons (504) are used to erase the device. Formation of such a device includes forming a thin tunnel dielectric layer (102) that may be less than 3.5 nanometers. When the control gate electrode (204) of the memory device is negatively biased, the thinner tunnel dielectric (102) allows holes to migrate through the tunnel dielectric to positively charge the isolated storage elements (200). When the device is to be erased, the control gate electrode (204) is positively biased, and rather than forcing the holes back across the tunnel dielectric, electrons present in the channel (402) are pulled through the tunnel dielectric where they recombine with the holes in the floating gate such that the stored positive charge is substantially neutralized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.