Flexible architecture for an embedded interrupt controller
US6401154B1 · kind B1 · utility
39Cited by
2References
39Claims
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Key dates
| Filing date | May 5, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2422
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable interrupt controller arrangement is provided including a multiple number of selectably enabled programmable interrupt controllers along with a multi-channel switch matrix. A scalable number of interrupt sources can be routed to any particular interrupt request line. In addition, from the same architecture, multiple interrupt sources are allowed to share any one of the interrupt request lines. Interrupt signals are routed via the switch matrix under software control. PC/AT compatibility is achieved by selectively disabling certain of the programmable interrupt controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.