High performance cost optimized memory
US6401167B1 · kind B1 · utility
113Cited by
10References
67Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1998 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2218
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.