Fault-tolerant architecture for in-circuit programming
US6401221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Aug 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for providing fault-tolerance for in-circuit programming systems. The invention operates by storing a minimal set of code to initialize the in-circuit programming process in a protected memory so that if the in-circuit programming process fails, the in-circuit programming process can be restarted from the protected memory. This type of fault-tolerance is especially important in systems which allow the code which accomplishes the in-circuit programming to be modified by the in-circuit programming process. One embodiment of the present invention provides a multiplexer to selectively switch between a normal boot code sequence and a protected boot code sequence, as well as a watchdog timer to monitor the in-circuit programming process to determine whether the in-circuit programming process is not progressing properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.