Method of manufacturing a semiconductor device
US6403426B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface 2 of the semiconductor body 1, and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. In a next step, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess 15 in the dielectric layer 14 at the area of the planned gate. Then, impurities are introduced via the recess 15 into the channel region 13 of the semiconductor body 1 in a self-registered way by using the dielectric layer 14, as a mask and an insulating layer is applied, fo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.