Complementary level shifting logic circuit with improved switching time
US6404229B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Oct 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary logic circuit is provided which provides improved switching times over known complementary logic circuits. The circuit includes a further n-type transistor connected in series between a p-type and an n-type transistor. This additional n-type transistor has its gate permanently connected to an upper supply voltage, Vdd. When switching occurs the n-type transistor is effectively open circuit. This allows the first n-type transistor to switch on by a substantial amount quite quickly without ‘fighting’ the presently conducting p-type transistor. When the first n-type transistor has been turned substantially on second transistor becomes conductive. Then the p-type transistor is substantially turned off and no longer opposes the turning on of the first n-type transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.