Fuse latch having multiplexers with reduced sizes and lower power consumption
US6404264B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 6, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.