Data processing device with memory coupling unit
US6405273B1 · kind B1 · utility
46Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.