System and method for recovery from address errors
US6405322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0796
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid. If the state of the cached line is valid and consistent, such as the “Modified uncached” (Mu) state in a MuMESI protocol, then the line may be written to main memory or provided to a snoop requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.