Deep sub-micron static timing analysis in the presence of crosstalk
US6405348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.