Method and apparatus for stacking IC devices
US6406940B1 · kind B1 · utility
3Cited by
9References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Aug 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for stacking semiconductor chips, including positioning a first chip and manipulating a second chip to a distance above the first chip that is no greater than a selected distance, and releasing the second chip to drop into a stacked configuration on the first chip. The selected distance is such as to avoid damage to either of the chips. Embodiments are disclosed for setting the drop distance of the second chip within the selected distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.