Poly resistor structure for damascene metal gate
US6406956B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A layer of gate oxide and polysilicon are deposited over the surface of a substrate, these layers are etched to create a dummy gate and a resistor. Spacers are formed on the dummy gate and the resistor, suitable impurities are implanted self-aligned with the dummy gate. A layer of dielectric is deposited and polished down to the surface of the dummy gate and the polysilicon resistor, the dummy gate is removed creating an opening in the layer of dielectric. A high-k dielectric is deposited over which a layer of metal is deposited, the surface of the layer of metal and high-k dielectric are polished down to the surface of the layer of dielectric leaving in place a metal gate electrode and a polysilicon resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.