Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets

US6406980B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Matthew J. Amatangelo · Orlando, US
• Christopher McCall Durham · Round Rock, US
• Peter Juergen Klim · Austin, US
• Stephen L. Runyon · Pflugerville, US

Key dates

• Filing date: Aug 24, 2000
• Grant date: Jun 18, 2002
• Expiry date: Dec 13, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/90

Abstract

A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.