Integrated circuit with in situ circuit arrangement for testing integrity of differential receiver inputs
US6407569B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Mar 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.