Fusible link configuration in integrated circuits

US6407586B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Helmut Fischer · Calw, DE
• Jochen Müller · Hersbruck, DE

Key dates

• Filing date: Feb 12, 2001
• Grant date: Jun 18, 2002
• Expiry date: Feb 12, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F1, F2, . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F1, F2, . . . ) and determines whether one or more of the fusible links (F1, F2, . . . ) is severed. One or more banks of the fusible links (F1, F2, . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F1, F2, . . . ) are located beside one another transversely with respect to the width direction of the bank.