Hierarchical access of test access ports in embedded core integrated circuits
US6408413B1 · kind B1 · utility
94Cited by
48References
11Claims
0Family size
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Inventor
Key dates
| Filing date | Feb 18, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit can have plural core circuits, each having a test access ports that is defined in IEEE Standar 1149.1. Access to and control of these ports is though a test linking moduled. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emudulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.