Method for remapping logic modules to resources of a programmable gate array
US6408422B1 · kind B1 · utility
35Cited by
49References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for remapping logic modules to resources of a programmable gate array. Connections are specified between at least two logic modules, wherein each module has a respective floorplan that includes a set of circuit elements. A first set of resources of the programmable gate array is compared to a second set of resources, wherein the second set of resources are those resources required by the sets of circuit elements. If the first set of resources covers the second set of resources, the floorplans of the logic modules are combined into a single floorplan that maps to the first set of resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.