Manufacture of dielectrically isolated integrated circuits
US6409829B1 · kind B1 · utility
2Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.