Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device
US6411543B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Jan 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.