Semiconductor memory device capable of reducing leakage current flowing into substrate
US6411560B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 14, 2001 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Nov 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.