Multiple-operand instruction in a two operand pipeline and processor employing the same
US6412063B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Apr 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the multiple-operand instruction. In one embodiment, the system includes: (1) node creation circuitry that creates at least first and second nodes for the multiple-operand instruction, the first node being empty and containing at least one of the operands and (2) node transmission circuitry, coupled to the node creation circuitry, that transmits the first and second nodes sequentially through the pipeline. All the operands are subsequently concurrently available within an execution stage of the pipeline for execution of the multiple-operand instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.