Backing out of a processor architectural state
US6412067B1 · kind B1 · utility
11Cited by
7References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1998 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Aug 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An executed first instruction having a first logical operand as a destination is retired. A register assigned to the first logical operand is identified to back out of an architectural state. The identifying may be performed when an executed second instruction having a second logical operand as a destination is ready to retire or is retired. The register may be assigned to a third logical operand for an instruction to be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.