Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

US6413802B1 · kind B1 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Chenming Hu · Alamo, US
• Tsu-Jae King · Fremont, US
• Vivek Subramanian · Redwood City, US
• Leland Chang · New York, US
• Xuejue Huang · Albany, US
• Yang-Kyu Choi · Seojong-myeon, KR
• Jakub Kedzierski · Peekskill, US
• Nick Lindert · Beaverton, US
• Jeffrey Bokor · Oakland, US
• Wen-Chin Lee · Baoshan, TW

Key dates

• Filing date: Oct 23, 2000
• Grant date: Jul 2, 2002
• Expiry date: Oct 23, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.