METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS

US6413824B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Amitava Chatterjee · Plano, US
• Alec J. Morton · Plano, US
• Mark S. Rodder · Dallas, US
• Taylor R. Efland · Richardson, US
• Chin-Yu Tsai · Plano, US
• James R. Hellums · Plano, US

Key dates

• Filing date: Jun 8, 2000
• Grant date: Jul 2, 2002
• Expiry date: Jun 8, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).