Single electron transistor using porous silicon
US6414333B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/937
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.