Thin-layer silicon-on-insulator (SOI) high-voltage device structure

US6414365B1 · kind B1 · utility

Assignee

• KONINKLIJKE PHILIPS ELECTRONICS NV · NL

Inventors

• Ted Letavic · Putnam Valley, US
• Mark Simpson · Houston, US

Key dates

• Filing date: Oct 1, 2001
• Grant date: Jul 2, 2002
• Expiry date: Oct 1, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

A thin layer SOI high-voltage device in which the drift charge is depleted using a three-dimensional MOS capacitor structure. The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes. Each SOI stripe is individually circumscribed longitudinally by a dielectric layer wherein each dielectric layer is longitudinally circumscribed by field plates of a conducting multi-capacitor field plate layer which is electrically shorted to the substrate. The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe and its encapsulating field plates.