Alignment pedestals in an LDMOS power package
US6414389B1 · kind B1 · utility
11Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or impedance matching capacitors, relative to the substrate surface. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.