Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit
US6414530B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 11, 2001 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Apr 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.