Integrated passive components and package with posts
US6414585B1 · kind B1 · utility
8Cited by
20References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1997 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | May 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.