Integrated memory with interblock redundancy
US6414886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2001 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.