Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
US6415353B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array requiring periodic refresh operations is controlled such that the refresh operations do not require explicit control signaling or handshake communication between the memory array and a memory controller. External accesses and refresh operations are handled such that refresh operations do not interfere with external accesses under any conditions. A multi-bank refresh scheme reduces the number of collisions between refresh operations and external accesses. A read buffer is used to buffer read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. The memory array, read buffer and write buffer can be constructed of DRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.