Method for forming gate electrode for a semiconductor device
US6417055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2001 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Jul 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.