Process for forming a dual damascene bond pad structure over active circuitry
US6417087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.