Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit
US6417715B2 · kind B2 · utility
51Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.