Method of programming and erasing non-volatile memory cells
US6418060B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2002 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Jan 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of selectively programming an individual memory cell of a non-volatile memory array. The non-volatile memory array is an array of memory cells. Each memory cell is made up of an ONO gate built on a substrate, which also acts as a well. On one side of the gate is a diffusion drain encompassed by a localized well region set in the well. On the other side of the gate is a diffusion source set in the well. When operated, appropriate voltages are applied to the source, the gate, the drain, and the localized well region to program or erase the non-volatile memory. The designed localized well region prevents an induction current in the unselected gates of the array, allowing for better selectivity and performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.