Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory
US6418062B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Mar 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of stably and uniformly erasing a non-volatile memory or memory array in a gate insulator in which carrier-trapping sites for carrier storage are furnished is described. A first method of the invention is the application of a discharge pulse(s) to a gate after erasure where the discharge pulse(s) discharges unstable holes injected into the gate insulator. A second method of the invention is injection of electrons into the trap sites of all the cells in a memory array to be erased before erasure. This makes Vth distribution across the memory array uniform after erasure. A third method of the invention is a reduced bias approach to erase stably the electrons stored in the trap sites. This includes not only literally “erase,” but also “annihilate or neutralize” trapped electron charge by hole charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.