Halo LSI, Inc.
57Patents
15Active
57Granted
39Portfolio score
Filing activity: Nov 30, 2000 → Apr 4, 2014 · 13 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6670240B2 | Twin NAND device structure, array operations and fabrication method | Electricity | 70 | Expired |
| US6707079B2 | Twin MONOS cell fabrication method and array organization | Emerging Cross-Sectional Technologies | 59 | Expired |
| US6914791B1 | High efficiency triple well charge pump circuit | Electricity | 38 | Expired |
| US6459622B1 | Twin MONOS memory cell usage for wide program | Physics | 35 | Expired |
| US6756271B1 | Simplified twin monos fabrication method with three extra masks to standard CMOS | Emerging Cross-Sectional Technologies | 30 | Expired |
| US7031192B1 | Non-volatile semiconductor memory and driving method | Physics | 23 | Expired |
| US6418062B1 | Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory | Physics | 21 | Expired |
| US6735118B2 | CG-WL voltage boosting scheme for twin MONOS | Physics | 20 | Expired |
| US6999345B1 | Method of sense and program verify without a reference cell for non-volatile semiconductor memory | Physics | 19 | Expired |
| US6549463B2 | Fast program to program verify method | Physics | 17 | Expired |
| US6900098B1 | Twin insulator charge storage device operation and its fabrication method | Electricity | 16 | Expired |
| US6876596B1 | Decoder circuit with function of plural series bit line selection | Physics | 16 | Expired |
| US6759290B2 | Stitch and select implementation in twin MONOS array | Electricity | 16 | Expired |
| US6807105B2 | Fast program to program verify method | Physics | 14 | Expired |
| US6542412B2 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Electricity | 13 | Expired |
| US6567314B1 | Data programming implementation for high efficiency CHE injection | Physics | 13 | Expired |
| US6714456B1 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Electricity | 12 | Expired |
| US6825084B2 | Twin NAND device structure, array operations and fabrication method | Electricity | 12 | Expired |
| US6631088B2 | Twin MONOS array metal bit organization and single cell operation | Physics | 12 | Expired |
| US7006378B1 | Array architecture and operation methods for a nonvolatile memory | Physics | 11 | Expired |
| US6580116B2 | Double sidewall short channel split gate flash memory | Electricity | 9 | Expired |
| US6631089B1 | Bit line decoding scheme and circuit for dual bit memory array | Physics | 8 | Expired |
| US6636438B2 | Control gate decoder for twin MONOS memory with two bit erase capability | Physics | 8 | Expired |
| US6643172B2 | Bit line decoding scheme and circuit for dual bit memory with a dual bit selection | Physics | 7 | Expired |
| US7394703B2 | Twin insulator charge storage device operation and its fabrication method | Electricity | 7 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.