Hierarchical fully-associative-translation lookaside buffer structure
US6418521B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1998 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Dec 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.