Translation lookaside buffer for virtual memory systems

US6418522B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ute Gaertner · Schenefeld, DE
• John D. Macdougall · Westborough, US
• Erwin Pfeffer · Eppelheim, DE
• Kerstin Claudia Schelm · Stuttgart, DE

Key dates

• Filing date: Feb 11, 2000
• Grant date: Jul 9, 2002
• Expiry date: Feb 11, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/681
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB s…