Erwin Pfeffer
55Patents
15h-index
44Co-inventors
84Inventor score
Filing activity: May 26, 1983 → Jun 20, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5761734A | Token-based serialisation of instructions in a multiprocessor system | Physics | 219 | Expired |
| US4570180A | Method for automatic optical inspection | Physics | 88 | Expired |
| US6418522B1 | Translation lookaside buffer for virtual memory systems | Physics | 59 | Expired |
| US7197601B2 | Method, system and program product for invalidating a range of selected storage translation table entries | Physics | 59 | Expired |
| US7284100B2 | Invalidating storage, clearing buffer entries, and an instruction therefor | Physics | 57 | Expired |
| US6996698B2 | Blocking processing restrictions based on addresses | Physics | 34 | Expired |
| US8103851B2 | Dynamic address translation with translation table entry format control for indentifying format of the translation table entry | Physics | 28 | Active |
| US8452942B2 | Invalidating a range of two or more translation table entries and instruction therefore | Physics | 22 | Active |
| US8041923B2 | Load page table entry address instruction execution based on an address translation format control field | Physics | 22 | Active |
| US8117417B2 | Dynamic address translation with change record override | Physics | 21 | Active |
| US8151085B2 | Method for address translation in virtual machines | Physics | 20 | Active |
| US8166239B2 | Translation lookaside buffer and related method and program product utilized for virtual addresses | Physics | 19 | Active |
| US7020761B2 | Blocking processing restrictions based on page indices | Physics | 16 | Expired |
| US6108771A | Register renaming with a pool of physical registers | Physics | 16 | Expired |
| US8037278B2 | Dynamic address translation with format control | Physics | 15 | Active |
| US5996063A | Management of both renamed and architected registers in a superscalar computer system | Physics | 15 | Expired |
| US6237076A | Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instruction | Physics | 13 | Expired |
| US7530067B2 | Filtering processor requests based on identifiers | Physics | 13 | Active |
| US8019964B2 | Dynamic address translation with DAT protection | Physics | 12 | Active |
| US6766434B2 | Method for sharing a translation lookaside buffer between CPUs | Physics | 11 | Expired |
| US7281115B2 | Method, system and program product for clearing selected storage translation buffer entries | Physics | 9 | Expired |
| US8041922B2 | Enhanced dynamic address translation with load real address function | Physics | 9 | Active |
| US10241910B2 | Creating a dynamic address translation with translation exception qualifiers | Physics | 7 | Active |
| US9092351B2 | Creating a dynamic address translation with translation exception qualifier | Physics | 7 | Active |
| US8930673B2 | Load page table entry address instruction execution based on an address translation format control field | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.