Self-aligned etch-stop layer formation for semiconductor devices
US6420273B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Sep 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for self-aligned processing of semiconductor device features is disclosed. This technique includes the formation of a semiconductor device with transistor gates having a polysilicon member that extends from the plane of a semiconductor substrate. A coating is deposited on the gates and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the gates without lithographic processing. A recess is formed in the exposed polysilicon surface and at least partially filled with an etch stop material such as silicon nitride. Silicidation of the polysilicon member to form a silicide layer in the recess or a selective chemical vapor deposition on the bottom of the recess with an appropriate metal may be performed before filling the recess with the etch stop material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.