Inventor · Fremont, CA, US

Xi-Wei Lin

80Patents
17h-index
34Co-inventors
84Inventor score

Filing activity: Jan 16, 1997 → Sep 9, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US7895548B2 Filler cells for design optimization in a place-and-route system Electricity 118 Active
US7926018B2 Method and apparatus for generating a layout for a transistor Physics 106 Active
US5883011A Method of removing an inorganic antireflective coating from a semiconductor substrate Physics 77 Expired
US5854510A Low power programmable fuse structures Electricity 75 Expired
US5882998A Low power programmable fuse structures and methods for making the same Electricity 59 Expired
US5953612A Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device Electricity 34 Expired
US6207543A Metallization technique for gate electrodes and local interconnects Electricity 33 Expired
US7484198B2 Managing integrated circuit stress using dummy diffusion regions Electricity 33 Active
US5834356A Method of making high resistive structures in salicided process semiconductor devices Electricity 30 Expired
US7542891B2 Method of correlating silicon stress to device instance parameters for circuit simulation Physics 28 Active
US6074921A Self-aligned processing of semiconductor device features Electricity 26 Expired
US7681164B2 Method and apparatus for placing an integrated circuit device within an integrated circuit layout Physics 26 Active
US5933739A Self-aligned silicidation structure and method of formation thereof Electricity 21 Expired
US6093656A Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device Electricity 19 Expired
US6143613A Selective exclusion of silicide formation to make polysilicon resistors Electricity 19 Expired
US5880006A Method for fabrication of a semiconductor device Electricity 18 Expired
US6420273B1 Self-aligned etch-stop layer formation for semiconductor devices Electricity 17 Expired
US9547740B2 Methods for fabricating high-density integrated circuit devices Electricity 16 Active
US5985749A Method of forming a via hole structure including CVD tungsten silicide barrier layer Electricity 16 Expired
US5963784A Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device Electricity 16 Expired
US7600207B2 Stress-managed revision of integrated circuit layouts Electricity 15 Active
US8086990B2 Method of correlating silicon stress to device instance parameters for circuit simulation Physics 14 Active
US6150266A Local interconnect formed using silicon spacer Electricity 13 Expired
US8964453B2 SRAM layouts Electricity 13 Active
US6218303A Via formation using oxide reduction of underlying copper Electricity 13 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.