Three device DRAM cell with integrated capacitor and local interconnect
US6420746B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1998 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Oct 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.