Semiconductor integrated circuit device capable of self-analyzing redundancy replacement adapting to capacities of plural memory circuits integrated therein
US6421286B1 · kind B1 · utility
62Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.