Semiconductor memory, and memory access method
US6421292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the semiconductor memory, a refresh signal is generated and the refresh operation is performed based on the refresh signal. Parity is generated when data is written and the generated parity is stored. When the refresh operation and a usual data read or write operation overlap, data in a memory cell which cannot be read because the refresh operation is given priority is determined based on the parity. Data which cannot be written because the refresh operation is given priority is held temporarily in a write data buffer. When the refresh operation is not overlapped for the usual data read or write operation, the data held in the write data buffer is rewritten in a corresponding memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.