Buffer memory configuration having a memory between a USB and a CPU

US6421770B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Martin Huch · Hersbruck, DE
• Jens Barrenscheen · Munich, DE
• Gunther Fenzl · Höhenkirchen-Siegertsbrunn, DE

Key dates

• Filing date: Jul 21, 1998
• Grant date: Jul 16, 2002
• Expiry date: Jul 21, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F5/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory itself. The first half of the memory defines a first memory page and the second half of the memory defines a second memory page, and each address in the address space is assigned exactly one memory location on each of the memory pages. A memory management unit generates a first significant bit which assigns in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page. The buffer memory architecture enables the memory independently to manage the data to be transferred. The two memory pages serve to decouple the central processing unit CPU and the bus. Both memory pages are virtually visible to the user but only one of the memory pages can ever be addressed for data transfer. Consequently, overlapping of the writing cycles is avoided by arranging the transmitted data and the data to be read out in separate areas of the memory.