PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor
US6423592B1 · kind B1 · utility
25Cited by
15References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT which has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified as a three-layer-one-step patterning process and can be applied to a capacitor-on-plug structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.