Shan Sun
36Patents
8h-index
42Co-inventors
75Inventor score
Filing activity: Apr 15, 1998 → May 4, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6495413B2 | Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits | Electricity | 26 | Expired |
| US6423592B1 | PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor | Electricity | 25 | Expired |
| US6238933A | Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors | Electricity | 22 | Expired |
| US9514797B1 | Hybrid reference generation for ferroelectric random access memory | Electricity | 19 | Active |
| US6830938B1 | Method for improving retention reliability of ferroelectric RAM | Electricity | 16 | Expired |
| US10074422B1 | 2T1C ferro-electric random access memory cell | Physics | 14 | Active |
| US6203608A | Ferroelectric thin films and solutions: compositions | Electricity | 10 | Expired |
| US6674633B2 | Process for producing a strontium ruthenium oxide protective layer on a top electrode | Electricity | 9 | Expired |
| US6627930B1 | Ferroelectric thin film capacitors having multi-layered crystallographic textures | Electricity | 8 | Expired |
| US7116572B2 | Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory | Physics | 7 | Expired |
| US7313010B2 | Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory | Physics | 6 | Active |
| US8916434B2 | Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process | Electricity | 6 | Active |
| US8552515B2 | Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps | Electricity | 5 | Active |
| US8518792B2 | Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure | Electricity | 5 | Active |
| US9305995B1 | Methods of fabricating an F-RAM | Electricity | 5 | Active |
| US6617626B2 | Ferroelectric semiconductor memory device and a fabrication process thereof | Electricity | 3 | Expired |
| US9515075B1 | Method for fabricating ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier | Electricity | 2 | Active |
| US9111944B2 | Method of fabricating a ferroelectric capacitor | Electricity | 2 | Active |
| US9318693B2 | Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure | Electricity | 1 | Active |
| US9548348B2 | Methods of fabricating an F-RAM | Electricity | 1 | Active |
| US9624094B1 | Hydrogen barriers in a copper interconnect process | Electricity | 1 | Active |
| US8081500B2 | Method for mitigating imprint in a ferroelectric memory | Physics | 1 | Active |
| US6777287B2 | Ferroelectric semiconductor memory device and a fabrication process thereof | Electricity | 1 | Expired |
| US10304731B2 | Damascene oxygen barrier and hydrogen barrier for ferroelectric random-access memory | Electricity | 0 | Active |
| US9646976B2 | Ferroelectric random-access memory with pre-patterned oxygen barrier | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.