Method for forming memory array and periphery contacts using a same mask
US6423627B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Contacts for an electronic device are formed by providing a substrate (12) that has at least two access line structures (16) for a memory array (14) and a periphery structure (20) for a peripheral circuit (18) to the memory array (14). A first insulative layer (40) is formed outwardly of the substrate (12), the access line structures (16), and the periphery structure (20). A contact area of the periphery structure (20) is exposed through the first insulative layer (40) while maintaining the first insulative layer (40) over at least a contact overlap portion (48) of the access line structures (16). A second insulative layer (60) is formed outwardly of the substrate (12), the access line structures (16), the periphery structure (20), and the first insulative layer (40). A self-aligned contact hole (70) overlapping the contact overlap portion (48) of the access line structures (16) and a periphery contact hole (72) overlapping the contact area (46) of the periphery structure (20) are formed through the second insulative layer (60) with a same mask (74). A self-aligned contact (80) is formed in the self-aligned contact hole (70) and a periphery contact (82) is formed in the periphery c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.